Electrical isolation of semiconductor integrated transistors from one another can be achieved by laterally (in the plane of the wafer) isolating "active" regions of the device with insulating material. Two techniques are common: 1) selectively oxidizing wafer silicon surrounding the active region (known as "LOCOS" or Local Oxidation of Silicon), or 2) depositing insulating material, such as silicon oxide around the active region. In the latter, it is known to form "trenches" around the active region, and to fill the trenches with oxide. This is referred to as Recessed Oxide Isolation (ROI). The oxide-filled trenches extend into the substrate to a depth of from a few hundred Angstroms (.ANG.) to a few microns (.mu.m). One such technique involves filling the trenches with Low-Temperature Oxide (LTO). In the main hereinafter, techniques of planarizing trenches, such as those filled with LTO, are discussed.
FIG. 1 shows a semiconductor device 10, at an intermediate fabrication stage. A substrate 12 has had trenches 14 (one trench illustrated) etched into its otherwise planar top surface, and the trenches 14 surround active, doped regions 16 (two active regions illustrated) of the semiconductor device. Since the active regions 16 are more elevated than the trenches 14, they are sometimes referred to as "islands".
In the process of forming the trenches 14, typically a patterned trench mask layer 18, of a relatively hard material such as silicon nitride, will have been applied with openings allowing for the etching of the trenches. As illustrated, the trench mask material 18 covers the islands 16, and the openings in the trench mask are vertically aligned with the trenches 14. In order to fill the trenches 14, an insulating material 20, such as silicon dioxide, is blanket deposited over the entire trench mask, and overfills the trenches, thereby creating an irregular top surface topography having a trough 22. For purposes of the discussion that follows, the trough 22 can be considered to be a trench in the layer 20. The excess insulating material 20 overlying the active regions 16 must be removed, and in the process of removing same, it is advantageous to planarize the trenches 14 so that the trench-fill material 20 is flush with the diffusion regions 16. (The mask 18 will be stripped away to allow for further fabrication steps.) FIG. 1 shows the semiconductor device 10 at this stage of fabrication - ready to have the excess trench-fill material 20 removed, and preferably planarized.
It is often desirable to smooth, or planarize, the top surface of the device after the insulating layer has been applied, prior to further process steps which may include various levels of metallization. In some cases, polishing techniques are employed to remove excess material over the island areas, leaving either a thin, planarized insulating layer (20), or leaving insulating material only in the trenches (14). In the latter case, the trench mask 18 conveniently acts as an polishing stop, since it (e.g., nitride) typically is much harder than the material being removed (e.g., oxide).
FIG. 2 shows the semiconductor device 10 of FIG. 1, after planarization. It can easily be seen that isolation oxide 20 remains only in the trenches 14 between active regions 16.
It should be understood that additional process steps, other than those described above, may be employed in the fabrication of trench isolation structures, such as creating an ion-implanted layer and an adhesion layer in the trench. These additional steps are not particularly germane to the present invention, and are omitted from further discussion for the sake of clarity.
A problem with planarization (by polishing) of trench structures, unaddressed by the prior art and of considerable importance, is that depending upon the size of a trench (e.g., 22), trench-fill material (e.g., oxide) may be "prematurely" removed from inside the trench, which would defeat the purpose of planarization. In other words, it is antithetical to planarization to have material being removed from within the trench at the same time that material without the trench is being removed.
FIGS. 3 and 4 graphically illustrate this point. As shown, a semiconductor device 30 includes a substrate 32 with trenches 34a and 34b formed therein, resulting in "islands" 36a, 36b and 36c between adjacent trenches. The trenches 34a and 34b are overfilled with oxide 38. As expected, the top surface of the blanket oxide 38 exhibits an irregular topography, following (to some extent) the topography of the trenched substrate, with commensurate troughs 40 and 42. The problem of planarizing trenches, i.e. avoiding prematurely gouging the trench bottom, is exacerbated when there are trenches having different sizes, namely different widths. (In a generalized case, the depths of all trenches and troughs tends to be uniform.) In this case, the trench 34a is narrower than the trench 34b, and the trough 40 is narrower than the trough 42.
FIG. 3 sets forth dimensions of interest, namely:
- t0, which is the initial thickness of the oxide 38. After removal of excess oxide, t0 will be zero over the islands 36 (a,b,c). For purposes of this discussion, t0 is assumed to be equal both within and without the trenches; PA1 - t1, which is the in-process thickness of the oxide 38, after partial removal of excess oxide; PA1 - t2, which is the in-process thickness of the trench fill material within the wide trench 34b; PA1 - W.sub.s, which is the width of the narrow trench 32; PA1 - W.sub.l, which is the width of the wide trench 34; and PA1 - h, which is the initial depth of the "feature" in this case of the trenches 40 and 42 sought to be planarized. PA1 a) an already planar surface (not illustrated, but which would exist in the case of t2=t1+h or PA1 b) having a perfectly flat and stiff polishing pad (which hardly represents r&ality).
In an "idealized" case, the troughs 40 and 42 also have widths W.sub.s and W.sub.l, respectively.
As illustrated in FIG. 4, a polishing pad 44 has an irregular surface, illustrated herein as features 46a and 46b. These pad features are simply surface irregularities. The pad carries abrasive particles (not illustrated) for polishing the semiconductor device 30, and these particles are typically much smaller than the trench width. As illustrated, the pad features tend to be larger than the trench widths. Because the pad 44 is resilient, its abrasive surface will tend to remove material from the bottom of a relatively wide trench (e.g., 42), without removing material from the bottom of a relatively narrow trench (e.g., 40). This will result from the fact that the polishing pad is not infinitely stiff, but rather is compliant and can deflect into wide trenches.
Returning to FIG. 3, the top surface topography prior to polishing is shown by the solid line 48, and the top surface topography after partial polishing is shown by the dashed line 50. Evidently, if during removal of material (t0-t1) from over the islands the polishing pad removes material (t0-t2) from within the wide trench (42), the object of planarization would be defeated, and even exacerbated as polishing continues.
Another problem is measuring the effectiveness of polishing.
Another problem is polishing where trenches having a wide range of widths is involved.
Another problem is that polishing is slow, compared to etching.